Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved, such that multiple ICs may be vertically stacked in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). An alternative packaging technique, referred to as a 2.5D package may use an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more dies to a PCB. A plurality of IC chips, which may be of heterogeneous technologies, are mounted on the interposer. Connections among the various ICs are routed through conductive patterns in the interposer. Interposers affect the operating characteristics of the ICs that are bonded or otherwise coupled to the interposer due to the resistance and capacitance (“RC”) of the semiconductor substrate.
Both 2.5D and 3D IC packages include the use of through substrate vias (TSV), also referred to as through-silicon-vias, in the case of silicon-based dies. The inclusion of TSV increases the complexity of semiconductor fabrication and packaging.